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| FM1808 256Kb Bytewide FRAM Memory Features 256Kbit Ferroelectric Nonvolatile RAM * Organized as 32,768 x 8 bits * High Endurance 10 Billion (1010) Read/Writes * 10 year Data Retention * NoDelayTM Writes * Advanced High-Reliability Ferroelectric Process Superior to BBSRAM Modules * No Battery Concerns * Monolithic Reliability * True Surface Mount Solution, No Rework Steps * Superior for Moisture, Shock, and Vibration * Resistant to Negative Voltage Undershoots SRAM & EEPROM Compatible * JEDEC 32Kx8 SRAM & EEPROM pinout * 70 ns Access Time * 130 ns Cycle Time Low Power Operation * 25 mA Active Current * 20 A Standby Current Industry Standard Configuration * Industrial Temperature -40 C to +85 C * 28-pin SOIC or DIP Description The FM1808 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile but operates in other respects as a RAM. It provides data retention for 10 years while eliminating the reliability concerns, functional disadvantages and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make FRAM superior to other types of nonvolatile memory. In-system operation of the FM1808 is very similar to other RAM devices. Minimum read- and writecycle times are equal. The FRAM memory, however, is nonvolatile due to its unique ferroelectric memory process. Unlike BBSRAM, the FM1808 is a truly monolithic nonvolatile memory. It provides the same functional benefits of a fast write without the disadvantages associated with modules and batteries or hybrid memory solutions. These capabilities make the FM1808 ideal for nonvolatile memory applications requiring frequent or rapid writes in a bytewide environment. The availability of a true surface-mount package improves the manufacturability of new designs, while the DIP package facilitates simple design retrofits. Device specifications are guaranteed over an industrial temperature range of -40C to +85C. Pin Configuration A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 Ordering Information FM1808-70-P 70 ns access, 28-pin plastic DIP FM1808-70-S 70 ns access, 28-pin SOIC This product conforms to specifications per the terms of the Ramt ron standard warranty. Production processing does not necessarily include testing of all parameters. Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058 www.ramtron.com Rev. 2.3 May 2003 Page 1 of 12 FM1808 A10-A14 Block Decoder A0-A14 Address Latch A0-A7 Row Decoder 32,768 x 8 FRAM Array CE A8-A9 Column Decoder WE OE Control Logic I/O Latch Bus Driver DQ0-7 Figure 1. Block Diagram Pin Description Pin Name A0-A14 DQ0-7 /CE Type Input I/O Input /OE /WE VDD VSS Input Input Supply Supply Description Address: The 15 address lines select one of 32,768 bytes in the FRAM array. The address value is latched on the falling edge of /CE. Data: 8-bit bi-directional data bus for accessing the FRAM array. Chip Enable: /CE selects the device when low. Asserting /CE low causes the address to be latched internally. Address changes that occur after /CE goes low will be ignored until the next falling edge occurs. Output Enable: Asserting /OE low causes the FM1808 to drive the data bus when valid data is available. Deasserting /OE high causes the DQ pins to be tri-stated. Write Enable: Asserting /WE low causes the FM1808 to write the contents of the data bus to the address location latched by the falling edge of /CE. Supply Voltage: 5V Ground Functional Truth Table /CE /WE H X X L H L Rev. 2.3 May 2003 Function Standby/Precharge Latch Address (and Begin Write if /WE=low) Read Write Note: The /OE pin controls only the DQ output buffers. Page 2 of 12 FM1808 Overview The FM1808 is a bytewide FRAM memory. The memory array is logically organized as 32,768 x 8 and is accessed using an industry standard parallel interface. All data written to the part is immediately nonvolatile with no delay. Functional operation of the FRAM memory is the same as SRAM type devices, except the FM1808 requires a falling edge of /CE to start each memory cycle. Read Operation A read operation begins on the falling edge of /CE. At this time, the address bits are latched and a memory cycle is initiated. Once started, a full memory cycle must be completed internally even if /CE goes inactive. Data becomes available on the bus after the access time has been satisfied. After the address has been latched, the address value may be changed upon satisfying the hold time parameter. Unlike an SRAM, changing address values will have no effect on the memory operation after the address is latched. The FM1808 will drive the data bus when /OE is asserted low. If /OE is asserted after the memory access time has been satisfied, the data bus will be driven with valid data. If /OE is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. When /OE is inactive the data bus will remain tri-stated. Write Operation Writes occur in the FM1808 in the same time interval as reads. The FM1808 supports both /CEand /WE-controlled write cycles. In all cases, the address is latched on the falling edge of /CE. In a /CE controlled write, the /WE signal is asserted prior to beginning the memory cycle. That is, /WE is low when /CE falls. In this case, the part begins the memory cycle as a write. The FM1808 will not drive the data bus regardless of the state of /OE. In a /WE controlled write, the memory cycle begins on the falling edge of /CE. The /WE signal falls after the falling edge of /CE. Therefore, the memory cycle begins as a read. The data bus will be driven according to the state of /OE until /WE falls. The timing of both /CE- and /WE-controlled write cycles is shown in the electrical specifications. Write access to the array begins asynchronously after the memory cycle is initiated. The write access terminates on the rising edge of /WE or /CE, whichever is first. Data set-up time, as shown in the electrical specifications, indicates the interval during which data cannot change prior to the end of the write access. Unlike other truly nonvolatile memory technologies, there is no write delay with FRAM. Since the read Page 3 of 12 Memory Architecture Users access 32,768 memory locations each with 8 data bits through a parallel interface. The complete 15-bit address specifies each of the 32,768 bytes uniquely. Internally, the memory array is organized into 32 blocks of 8Kb each. The 5 most-significant address lines decode one of 32 blocks. This block segmentation has no effect on operation, however the user may wish to group data into blocks by its endurance characteristics as explained on page 4. The cycle time is the same for read and write memory operations. This simplifies memory controller logic and timing circuits. Likewise the access time is the same for read and write memory operations. When /CE is deasserted high, a precharge operation begins, and is required of every memory cycle. Thus unlike SRAM, the access and cycle times are not equal. Writes occur immediately at the end of the access with no delay. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. Note that the FM1808 has no special power-down requirements. It will not block user access and it contains no power-management circuits other than a simple internal power-on reset. It is the user's responsibility to ensure that VDD remains within datasheet tolerances to prevent incorrect operation. Also proper voltage level and timing relationships between VDD and /CE must be maintained in powerup and power-down events. Memory Operation The FM1808 is designed to operate in a manner similar to other bytewide memory products. For users familiar with BBSRAM, the performance is comparable but the bytewide interface operates in a slightly different manner as described below. For users familiar with EEPROM, the obvious differences result from the higher write performance of FRAM technology including NoDelay writes and much higher write endurance. Rev. 2.3 May 2003 FM1808 and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Therefore, any operation including read or write can occur immediately following a write. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Precharge Operation The precharge operation is an internal condition that prepares the memory for a new access. All memory cycles consist of a memory access and a precharge. The precharge is initiated by deasserting the /CE pin high. It must remain high for at least the minimum precharge time t PC. The user determines the beginning of this operation since a precharge will not begin until /CE rises. However, the device has a maximum /CE low time specification that must be satisfied. battery. FRAM uses an inherently nonvolatile storage mechanism that requires no battery. It therefore eliminates these weaknesses. The major considerations in upgrading to FRAM follow: Construction Issues 1. Cost The cost of both the component and the manufacturing overhead of battery-backed SRAM is high. FRAM with its monolithic construction is inherently a lower cost solution. In addition, there is no `built-in' rework step required for battery attachment when using surface mount parts. Therefore assembly is streamlined and more cost effective. In the case of DIP battery-backed modules, the user is constrained to through-hole assembly techniques and a board wash using no water. 2. Humidity A typical battery-backed SRAM module is qualified at 60 C, 90% Rh, but under no bias and no pressure. These conditions are chosen because multicomponent assemblies are vulnerable to moisture and dirt. FRAM is qualified using HAST - highly accelerated stress test. This requires 120 C at 85% Rh, 24.4 psia at 5.5V. 3. System reliability Data integrity must be questioned when using a battery-backed SRAM. They are inherently vulnerable to shock and vibration. If the battery contact comes loose, data will be lost. In addition a negative voltage, even a momentary undershoot, on any pin of a battery-backed SRAM can cause data loss. The negative voltage causes current to be drawn directly from the battery. These momentary short circuits can greatly weaken a battery and reduce its capacity over time. In general, there is no way to monitor the lost battery capacity. Should an undershoot occur in a battery backed system during a power down, data can be lost immediately. 4. Space Certain disadvantages of battery-backed, such as susceptibility to shock, can be reduced by using the old fashioned DIP module. However, this alternative takes up board space, height, and dictates throughhole assembly. FRAM offers a true surface-mount solution that uses 25% of the board space. Endurance Internally, a FRAM operates with a read and restore mechanism. Therefore, each read and write cycle involves a change of state. The memory architecture is based on an array of rows and columns. Each read or write access causes an endurance cycle for an entire row. In the FM1808, a row is 32 bits wide. Every 4-byte boundary marks the beginning of a new row. Endurance can be optimized by ensuring frequently accessed data is located in different rows. Regardless, FRAM offers substantially higher write endurance than other nonvolatile memories. The rated endurance limit of 1010 cycles will allow 30 accesses per second to the same row for over 10 years. Applications As the first truly nonvolatile RAM, the FM1808 fits into many diverse applications. Clearly, its monolithic nature and high performance make it superior to battery-backed SRAM in many applications. This applications guide is intended to facilitate the transition from BBSRAM to FRAM. It is divided into two parts. First is a treatment of the advantages of FRAM memory compared with battery-backed SRAM. Second is a design guide, which highlights design considerations that should be reviewed in both retrofit and new design situations. FRAM Advantages Although battery-backed SRAM is a mature and established solution, it has many weaknesses. These stem directly or indirectly from the presence of the Rev. 2.3 May 2003 Direct Battery Issues 5. Field maintenance Page 4 of 12 FM1808 No matter how mature batteries become, they are a maintenance problem. They eventually must be replaced. Despite long life projections, it is impossible to know if any individual battery will last considering all of the factors that can degrade them. 6. Environmental Lithium batteries are widely regarded as an environmental problem. They are a potential fire hazard and proper disposal can be a burden. In addition, shipping of lithium batteries may be restricted. 7. Style! Backing up an SRAM with a battery is an oldfashioned approach. In many cases, such modules are the only through-hole component in sight. FRAM is the latest memory technology and it is changing the way systems are designed. FRAM is nonvolatile and writes fast -- no battery required. Rev. 2.3 May 2003 Page 5 of 12 FM1808 FRAM Design Considerations When designing with FRAM for the first time, users of SRAM will recognize a few minor differences. First, bytewide FRAM memories latch each address on the falling edge of chip enable. This allows the address bus to change after starting the memory access. Since every access latches the memory address on the falling edge of /CE, users cannot ground it as they might with SRAM. Users who are modifying existing designs to use FRAM should examine the memory controller for timing compatibility of address and control pins. Each memory access must be qualified with a low transition of /CE. In many cases, this is the only change required. An example of the signal relationships is shown in Figure 2 below. Also shown is a common SRAM signal relationship that will not work for the FM1808. The reason for /CE to strobe for each address is two fold: it latches the new address and creates the necessary precharge period while /CE is high. A second design consideration relates to the level of VDD during operation. Battery-backed SRAMs are forced to monitor VDD in order to switch to battery backup. They typically block user access below a certain VDD level in order to prevent loading the battery with current demand from an active SRAM. The user can be abruptly cut off from access to the nonvolatile memory in a power down situation with no warning or indication. FRAM memories do not need this system overhead. The memory will not block access at any VDD level. The user, however, should prevent the processor from accessing memory when VDD is out-oftolerance. The common design practice of holding a processor in reset when V drops is adequate; no DD special provisions must be taken for FRAM design. Valid Strobing of /CE CE FRAM Signaling Address A1 A2 Data D1 D2 Invalid Strobing of /CE CE SRAM Signaling Address A1 A2 Data D1 D2 Figure 2. Chip Enable and Memory Address Relationships Rev. 2.3 May 2003 Page 6 of 12 FM1808 Electrical Specifications Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any pin with respect to VSS TSTG TLEAD Storage Temperature Lead Temperature (Soldering, 10 seconds) Ratings -1.0V to +7.0V -1.0V to +7.0V and VIN < VDD+1.0V -55C to + 125C 300 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units VDD Power Supply 4.5 5.0 5.5 V IDD1 VDD Supply Current (180 ns cycle) 7 15 mA IDD2 VDD Supply Current (130 ns cycle) 12 25 mA ISB1 Standby Current - TTL input levels 400 A ISB2 Standby Current - CMOS input levels 7 20 A ILI Input Leakage Current 10 A ILO Output Leakage Current 10 A VIH Input High Voltage 2.0 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V VOH Output High Voltage (IOH = -2.0 mA) 2.4 V VOL Output Low Voltage (IOL = -4.2 mA) 0.4 V Notes 1. VDD = 5.5V, /CE cycling at minimum cycle time. All inputs at CMOS levels, all outputs unloaded. 2. VDD = 5.5V, /CE at VIH, All other pins at TTL levels. 3. VDD = 5.5V, /CE at VIH, All other pins at CMOS levels. 4. VIN, VOUT between VDD and VSS. Notes 1 1 2 3 4 4 Data Retention (VDD = 4.5V to 5.5V unless otherwise specified) Parameter Min Units Data Retention 10 years Notes 1 Notes The relationship between retention, temperature, and the associated reliability level is characterized in a separate reliability report. Rev. 2.3 May 2003 Page 7 of 12 FM1808 Read Cycle AC Parameters (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter -70 Min Max tCE Chip Enable Access Time (to data valid) 70 tCA Chip Enable Active Time 70 2,000 tRC Read Cycle Time 130 tPC Precharge Time 60 tAS Address Setup Time 4 tAH Address Hold Time 10 tOE Output Enable Access Time 10 tHZ Chip Enable to Output High-Z 15 tOHZ Output Enable to Output High-Z 15 Units ns ns ns ns ns ns ns ns ns Notes 3 1 1 Write Cycle AC Parameters (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter -70 Units Min Max tCA Chip Enable Active Time 70 2,000 ns tCW Chip Enable to Write High 70 ns tWC Write Cycle Time 130 ns tPC Precharge Time 60 ns tAS Address Setup Time 4 ns tAH Address Hold Time 10 ns tWP Write Enable Pulse Width 40 ns tDS Data Setup 30 ns tDH Data Hold 5 ns tWZ Write Enable Low to Output High Z 15 ns tWX Write Enable High to Output Driven 10 ns tHZ Chip Enable to Output High-Z 15 ns tWS Write Enable Setup 0 ns tWH Write Enable Hold 0 ns Notes 3 1 1 1 2 2 Notes 1 This parameter is periodically sampled and not 100% tested. 2 The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. There is no timing specification associated with this relationship. 3 The minimum address setup time is 0 ns when the device is operating above 0 C. Power Cycle Timing (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units tPU VDD(min) to First Access Start 1 S tPD Last Access Complete to VDD(min) 0 S Notes Rev. 2.3 May 2003 Page 8 of 12 FM1808 Capacitance (TA = 25 C, f=1.0 MHz, VDD = 5V) Symbol Parameter Min CI/O Input Output Capacitance CIN Input Capacitance AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels Max 8 6 Units pF pF Notes Equivalent AC Load Circuit 0 to 3V 10 ns 1.5V Read Cycle Timing tRC tC A tPC CE tA S tA H A0-14 tO E OE tO H Z DQ0-7 tC E tHZ Write Cycle Timing - /CE Controlled Timing tWC tC A tPC CE tA S tA H A0-14 tWS t WH WE OE tD S tDH DQ0-7 Rev. 2.3 May 2003 Page 9 of 12 FM1808 Write Cycle Timing - /WE Controlled Timing tWC tC A tPC CE tA S tA H tC W A0-14 tWS t WH tWP WE OE tWZ t WX DQ0-7 out tDS t DH DQ0-7 in Power Cycle Timing VDD VDD (min) t PD t PC VDD (min) t PU VIH (min) VIL (max) CE VIH (min) Rev. 2.3 May 2003 Page 10 of 12 FM1808 28-pin SOIC (JEDEC MS-013 variation AE) E H Pin 1 D A e B A1 .10 mm .004 in. h 45 L C Selected Dimensions For complete dimensions and notes, refer to JEDEC MS-013 Controlling dimensions in millimeters. Conversions to inches are not exact. Symbol A A1 B C D E e H h L Dim mm in. mm in. mm in. mm in. mm in. mm in. mm in. mm in. mm in. mm in. Min 2.35 0.0926 0.10 0.004 0.33 0.013 0.23 0.0091 17.70 0.6969 7.40 0.2914 Nom. Max 2.65 0.1043 0.30 0.0118 0.51 0.020 0.32 0.0125 18.10 0.7125 7.60 0.2992 1.27 BSC 0.050 BSC 10.00 0.394 0.25 0.010 .40 0.016 0 10.65 0.419 0.75 0.029 1.27 0.050 8 Rev. 2.3 May 2003 Page 11 of 12 FM1808 28-pin DIP JEDEC MS-011 E1 PIN 1 D E A2 A A1 D1 e B1 B L eA eB Selected Dimensions For complete dimensions and notes, refer to JEDEC MS-011 Controlling dimensions in inches. Conversions to millimeters are not exact. Symbol A A1 A2 B B1 D D1 E E1 e eA eB L Dim in. mm in. mm in. mm in. mm in. mm in. mm in. mm in. mm in. mm in. mm in. mm in. mm in. mm Min Nom. Max 0.250 6.35 0.015 0.39 0.125 3.18 0.014 0.356 0.030 0.77 1.380 35.1 0.005 0.13 0.600 15.24 0.485 12.32 0.100 BSC 2.54 BSC 0.600 BSC 15.24 BSC 0.195 4.95 0.022 0.558 0.070 1.77 1.565 39.7 0.625 15.87 0.580 14.73 0.115 2.93 0.700 17.78 0.200 5.08 Rev. 2.3 May 2003 Page 12 of 12 |
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